Neuromorphic circuits for nanoscale devices /
Nanoscale devices attracted significant research effort from the industry and academia due to their operation principals being based on different physical properties which provide advantages in the design of certain classes of circuits over conventional CMOS transistors. Neuromorphic Circuits for Na...
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| Main Authors: | , , , |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Gistrup, Denmark :
River Publishers,
[2019]
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| Series: | River Publishers series in biomedical engineering.
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| Subjects: | |
| Online Access: |
Full text (Emmanuel users only) |
MARC
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| 100 | 1 | |a Mazumder, Pinaki, |e author. | |
| 245 | 1 | 0 | |a Neuromorphic circuits for nanoscale devices / |c Pinaki Mazumder, Yalcin Yilmaz, Idongesit Ebong, Woo Hyung Lee. |
| 264 | 1 | |a Gistrup, Denmark : |b River Publishers, |c [2019] | |
| 300 | |a 1 online resource | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a River Publishers series in biomedical engineering | |
| 500 | |a 5.2.1 Lateral Inhibition | ||
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Front Cover; Half Title; Series Page -- RIVER PUBLISHERS SERIES IN BIOMEDICAL ENGINEERING; Title Page; Copyright Page; Contents; Preface; Acknowledgement; List of Contributors; List of Figures; List of Tables; List of Abbreviations; Chapter 1 -- Introduction; 1.1 Discovery; 1.2 The Missing Memristor; 1.2.1 Definitions; 1.2.2 DC Response of an Ideal Memristor; 1.2.3 AC Response of an Ideal Memristor; 1.2.4 AC Response of an Ideal Memristor: Higher Frequencies; 1.2.5 Some Further Observations; 1.2.5.1 Requirement 1: Nonlinearity; 1.2.5.2 Requirement 2: Continuous ' v. q | |
| 505 | 8 | |a 1.2.5.3 Requirement 3: Strictly monotonically increasing ' v. q1.2.6 Summary; 1.3 Memristive Devices and Systems; 1.3.1 Definitions; 1.3.2 Resistive Switching Mechanisms; 1.3.3 Transport of Mobile Ions; 1.3.4 Formation of Conduction Filaments; 1.3.5 Phase Change Transitions; 1.3.6 Resonant Tunneling Diodes; 1.3.7 Magnetoresistive Memory, Nanoparticles and Multi-State Devices; 1.3.7.1 Spin-transfer torque; 1.3.7.2 Nanoparticles; 1.3.7.3 Multi-state memories; 1.4 Neuromorphic Computing; 1.4.1 Memristive Synapse; 1.4.2 Memristive Neuron; 1.4.3 Memristive Neural Networks | |
| 505 | 8 | |a 1.4.3.1 Crossbar processing: Read1.4.3.2 Crossbar processing: Write; 1.4.3.3 Crossbar processing: Training; 1.5 Looking Forward; References; Chapter 2 -- Crossbar Memory Simulation and Performance Evaluation; 2.1 Introduction; 2.1.1 Motivation; 2.1.2 Contrast with Competing Technologies; 2.1.3 Amorphous Si Crossbar Memory Cell; 2.2 Structure; 2.2.1 Crossbar Modeling; 2.3 Write Strategy and Circuit Implementation; 2.4 Read Strategy and Circuit Implementation; 2.5 Memory Architecture; 2.6 Power Dissipation; 2.6.1 Power Estimation; 2.6.2 Analytical Modeling on Static Power; 2.7 Noise Analysis | |
| 505 | 8 | |a 2.8 Area Overhead2.8.1 Bank-based System Design; 2.9 Technology Comparison; References; Chapter 3 -- Memristor Digital Memory; 3.1 Introduction; 3.2 Adaptive Reading and Writing in Memristor Memory; 3.3 Simulation Results; 3.3.1 High State Simulation (HSS); 3.3.2 Background Resistance Sweep (BRS); 3.3.3 Minimum Resistance Sweep (MRS); 3.3.4 Diode Leakage Current (DLC); 3.3.5 Power Modeling; 3.4 Adaptive Methods Results and Discussion; 3.5 Chapter Summary; References; Chapter 4 -- Multi-Level Memory Architecture; 4.1 Introduction; 4.2 Multi-State Memory Architecture; 4.2.1 Architecture | |
| 505 | 8 | |a 4.2.2 Read/Write Circuitry4.2.3 Array Voltage Bias Scheme; 4.2.4 Read/Write Operations Flow; 4.2.5 State Derivations; 4.3 Read/Write Operations; 4.3.1 Read/Write Simulations; 4.3.2 Read Disturbances to the Neighboring Cells; 4.4 Effects of Variations; 4.4.1 Variations in Programming Voltage; 4.4.2 Variations in Series Resistance; 4.4.3 Reduced-Impact Read Scheme; 4.4.4 Resistance Distributions after Array Writes; 4.5 Conclusion; References; Chapter 5 -- Neuromorphic Building Blocks with Memristors; 5.1 Introduction; 5.2 Implementing Neuromorphic Functions with Memristors | |
| 520 | |a Nanoscale devices attracted significant research effort from the industry and academia due to their operation principals being based on different physical properties which provide advantages in the design of certain classes of circuits over conventional CMOS transistors. Neuromorphic Circuits for Nanoscale Devices contains recent research papers presented in various international conferences and journals to provide insight into how the operational principles of the nanoscale devices can be utilized for the design of neuromorphic circuits for various applications of non-volatile memory, neural network training/learning, and image processing. The topics discussed in the book include: * Nanoscale Crossbar Memory Design * Q-Learning and Value Iteration using Nanoscale Devices * Image Processing and Computer Vision Applications for Nanoscale Devices * Nanoscale Devices based Cellular Nonlinear/Neural Networks. | ||
| 588 | 0 | |a Online resource; title from digital title page (viewed on January 15, 2020). | |
| 650 | 0 | |a Nanoelectromechanical systems. | |
| 650 | 0 | |a Neuromorphics. | |
| 700 | 1 | |a Yilmaz, Yalcin, |e author. | |
| 700 | 1 | |a Ebong, Idongesit, |e author. | |
| 700 | 1 | |a Lee, Woo Hyung, |e author. | |
| 758 | |i has work: |a Neuromorphic circuits for nanoscale devices (Text) |1 https://id.oclc.org/worldcat/entity/E39PCGM4VKbky8G3GHH7Yv7Y6C |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Mazumder, Pinaki. |t Neuromorphic Circuits for Nanoscale Devices. |d Aalborg : River Publishers, ©2019 |z 9788770220606 |
| 830 | 0 | |a River Publishers series in biomedical engineering. | |
| 852 | |b Online |h ProQuest | ||
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